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Description
74LS109ANDual J K Flip Flop with Inverted K Input, Positive Edge Triggered Specifications Function Set(Preset) and Reset Type JK Type Output Type Complementary Number of Elements 2 Number of Bits per Element 1 Clock Frequency 33 MHz Max Propagation Delay @ V, Max CL 40ns @ 5V, 15pF Trigger Type Positive Edge Current Output High, Low 400A, 8mA Voltage Supply 4. 75V ~ 5. 25V Current Quiescent (Iq) 8 mA Operating Temperature 0C ~ 70C (TA) Mounting Type Through
Specifications
|
Function |
Set(Preset) and Reset |
|
Type |
JK Type |
|
Output Type |
Complementary |
|
Number of Elements |
2 |
|
Number of Bits per Element |
1 |
|
Clock Frequency |
33 MHz |
|
Max Propagation Delay @ V, Max CL |
40ns @ 5V, 15pF |
|
Trigger Type |
Positive Edge |
|
Current - Output High, Low |
400µA, 8mA |
|
Voltage - Supply |
4.75V ~ 5.25V |
|
Current - Quiescent (Iq) |
8 mA |
|
Operating Temperature |
0°C ~ 70°C (TA) |
|
Mounting Type |
Through Hole |
|
Supplier Device Package |
16-PDIP |
|
Package / Case |
16-DIP (0.300", 7.62mm) |
Additional Information
| Device | IC |
Shipping Notes
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